Tesla’s Dojo Is An Interesting CPU Design

What do you get when you cross a fashionable tremendous-scalar out-of-buy CPU main with additional standard microcontroller facets these types of as no digital memory, no memory cache, and no DDR or PCIe controllers? You get the Tesla Dojo, which Chips and Cheese recently did a deep dive on.

It starts off with a comparison to the IBM Cell processors. The Mobile of the mid-2000s highlighted one thing termed the SPE (Synergistic Processing Features). They had been more compact cores centered on vector processing or other specialized varieties of workloads. They didn’t obtain the major memory and experienced to be offered responsibilities by the absolutely showcased CPU. Dojo has 1.25MB of SRAM that it can use as performing memory with 5 ports, but it has no cache or digital memory. It employs DMA to get the facts it wants by means of a mesh system. The entrance conclusion pulls RISC-V-like (heavily MIPS-encouraged) guidance into a smaller instruction cache and decodes eight guidelines for every cycle.

Interestingly, the entrance stop aggressively prunes instructions this sort of as jumps or conditionals. Nevertheless, eliminated guidance aren’t tracked as a result of the pipeline. Recommendations are not tracked as a result of retirement, so for the duration of exceptions and debugging, and it’s unclear what the faulting instruction was as recommendations are retired out of buy.

Even with the vast entrance stop, there are just two ALUs and two AGUs. This makes perception as the aim of integer execution is mostly focused on management flow and logic. The precise computing horsepower is the vector and matrix execution pipelines. With 512-bit vectors and 8x8x4 matrices, each and every dojo main will come near to a total BF26 TFLOP. The result is anything that looks more like a microprocessor but is vast like a present day desktop CPU.

All these selections may well appear to be peculiar right until you stage back and glance at what Tesla is making an attempt to attain. They’re heading for the smallest doable core to healthy as several cores on the die as possible. Without having a cache, you do not will need any snoop filters or tags in memory to retain coherency. On TSMC’s 7nm course of action, the Dojo core and SRAM fit in 1.1 sq. millimeters. Over 71.1% of the die is put in on cores and SRAM (as opposed to 56% of the AMD Zeppelin). A one Dojo D1 die has 354 Dojo cores. As you can imagine, a Dojo die will have to communicate with an interface processor, which connects to the host computer by way of PCIe. Having said that, Dojo deployments usually have 25 dies, earning this a pretty scalable supercomputer.

If you are curious about peeling again the levels of a lot more compute cores, appear into Alder Lake.